View GA10JT12-247_8234478.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

GA10JT12-247 nov 2014 http://www.genesicsemi.com/commercial- sic/sic-junction-transistors/ pg1 of 11 s d g normally ? off silicon carbide junction transistor features package ? 175 c maximum operating temperature ? gate oxide free sic switch ? exceptional safe operating area ? excellent gain linearity ? temperature independent switching performance ? low output capacitance ? positive temperature coefficient of r ds,on ? suitable for connecting an anti-parallel diode ? to-247 ? advantages applications ? compatible with si mosfet/igbt gate drive ics ? > 20 s short-circuit withstand capability ? lowest-in-class conduction losses ? high circuit efficiency ? minimal input signal distortion ? high amplifier bandwidth ? ? hybrid electric vehicles (hev) ? solar inverters ? switched-mode power supply (smps) ? power factor correction (pfc) ? induction heating ? uninterruptible power supply (ups) ? motor drives table of contents section i: absolute maximum ratings ........................................................................................... ............... 1 ? section ii: static elect rical characteristics ................................................................................. .................. 2 ? section iii: dynamic elect rical charac teristics ............................................................................... ............. 2 ? section iv: figures ........................................................................................................... ............................... 3 ? section v: driving the ga10jt 12-247 ........................................................................................... ................ 7 ? section vi: packag e dimensions ................................................................................................ ................. 11 ? section vii: spice model para meters ........................................................................................... .............. 12 ? section i: absolute maximum ratings parameter symbol conditions value unit notes drain ? source voltage v ds v gs = 0 v 1200 v continuous drain current i d t c = 25c 25 a fig. 17 continuous drain current i d t c = 155c 10 a fig. 17 continuous gate current i g 1.3 a turn-off safe operating area rbsoa t vj = 175 o c, clamped inductive load i d,max = 10 @ v ds v dsmax a fig. 19 short circuit safe operating area scsoa t vj = 175 o c, i g = 1 a, v ds = 800 v, non repetitive >20 s reverse gate ? source voltage v sg 30 v reverse drain ? source voltage v sd 25 v power dissipation p tot t c = 25 c / 155 c, t p > 100 ms 170 / 22 w fig. 16 storage temperature t stg -55 to 175 c s g d d v ds = 1200 v r ds(on) = 120 m i d (tc = 25c) = 25 a i d (tc > 125c) = 10 a h fe (tc = 25c) = 80
GA10JT12-247 nov 2014 http://www.genesicsemi.com/commercial- sic/sic-junction-transistors/ pg2 of 11 section ii: static electrical characteristics a: on state b: off state c: thermal section iii: dynamic electrical characteristics a: capacitance and gate charge b: switching 1 1 ? all times are relative to the drain-source voltage v ds parameter symbol conditions value unit notes min. typical max. drain ? source on resistance r ds(on) i d = 10 a, t j = 25 c i d = 10 a, t j = 125 c i d = 10 a, t j = 175 c 120 164 208 m ? fig. 5 gate ? source saturation voltage v gs,sat i d = 10 a, i d /i g = 40, t j = 25 c i d = 10 a, i d /i g = 30, t j = 175 c 3.50 3.27 v fig. 7 dc current gain h fe v ds = 5 v, i d = 10 a, t j = 25 c v ds = 5 v, i d = 10 a, t j = 125 c v ds = 5 v, i d = 10 a, t j = 175 c 80 56 50 ? fig. 5 drain leakage current i dss v ds = 1200 v, v gs = 0 v, t j = 25 c v ds = 1200 v, v gs = 0 v, t j = 125 c v ds = 1200 v, v gs = 0 v, t j = 175 c 1 1 10 a fig. 8 gate leakage current i sg v sg = 20 v, t j = 25 c 20 na thermal resistance, junction - case r thjc 0.88 c/w fig. 20 parameter symbol conditions value unit notes min. typical max. input capacitance c iss v gs = 0 v, v ds = 800 v, f = 1 mhz 1403 pf fig. 9 reverse transfer/output capacitance c rss /c oss v ds = 800 v, f = 1 mhz 30 pf fig. 9 output capacitance stored energy e oss v gs = 0 v, v ds = 800 v, f = 1 mhz 9 j fig. 10 effective output capacitance, time related c oss,tr i d = constant, v gs = 0 v, v ds = 0?800 v 55 pf effective output capacitance, energy related c oss,er v gs = 0 v, v ds = 0?800 v 40 pf gate-source charge q gs v gs = -5?3 v 11 nc gate-drain charge q gd v gs = 0 v, v ds = 0?800 v 44 nc gate charge - total q g 55 nc internal gate resistance ? zero bias r g(int-zero) f = 1 mhz, v ac = 50 mv, v ds = 0 v, v gs = 0 v, t j = 175 oc 2.6 ? internal gate resistance ? on r g ( int-on ) v gs > 2.5 v, v ds = 0 v, t j = 175 oc 0.19 ? turn on delay time t d ( on ) t j = 25 oc, v ds = 800 v, i d = 10 a, resistive load refer to section v for additional driving information. 15 ns fall time, v ds t f 18 ns fig. 11, 13 turn off delay time t d ( off ) 22 ns rise time, v ds t r 13 ns fig. 12, 14 turn on delay time t d ( on ) t j = 175 oc, v ds = 800 v, i d = 10 a, resistive load 14 ns fall time, v ds t f 18 ns fig. 11 turn off delay time t d ( off ) 33 ns rise time, v ds t r 11 ns fig. 12 turn-on energy per pulse e on t j = 25 oc, v ds = 800 v, i d = 10 a, inductive load refer to section v. 181 j fig. 11, 13 turn-off energy per pulse e off 16 j fig. 12, 14 total switching energy e tot 197 j turn-on energy per pulse e on t j = 175 oc, v ds = 800 v, i d = 10 a, inductive load 192 j fig. 11 turn-off energy per pulse e off 11 j fig. 12 total switching energy e tot 203 j
GA10JT12-247 nov 2014 http://www.genesicsemi.com/commercial- sic/sic-junction-transistors/ pg3 of 11 section iv: figures a: static characteristic figures figure 1: typical output characteristics at 25 c figure 2: typical output characteristics at 125 c figure 3: typical output characteristics at 175 c figure 4: drain-source voltage vs. gate current figure 5: dc current gain and normalized on-resistance vs. temperature figure 6: dc current gain vs. drain current
GA10JT12-247 nov 2014 http://www.genesicsemi.com/commercial- sic/sic-junction-transistors/ pg4 of 11 figure 7: typical gate ? source saturation voltage figure 8: typical blocking characteristics b: dynamic characteristic figures figure 9: input, output, and reverse transfer capacitance figure 10: energy stored in output capacitance figure 11: typical switching times and turn on energy losses vs. temperature figure 12: typical switching times and turn off energy losses vs. temperature
GA10JT12-247 nov 2014 http://www.genesicsemi.com/commercial- sic/sic-junction-transistors/ pg5 of 11 figure 13: typical switching times and turn on energy losses vs. drain current figure 14: typical switching times and turn off energy losses vs. drain current c: device derating figures figure 15: typical hard switched device power loss vs. switching frequency 2 figure 16: power derating curve figure 17: drain current derating vs. temperature figure 18: forward bias safe operating area at t c = 25 o c 2 ? representative values based on device conduction and switching loss. actual losses will depend on gate drive conditions, dev ice load, and circuit topology.
GA10JT12-247 nov 2014 http://www.genesicsemi.com/commercial- sic/sic-junction-transistors/ pg6 of 11 figure 19: turn-off safe operating area figure 20: transient thermal impedance figure 21: drain current derating vs. pulse width
GA10JT12-247 nov 2014 http://www.genesicsemi.com/commercial- sic/sic-junction-transistors/ pg7 of 11 section v: driving the GA10JT12-247 drive topology gate drive power consumption switching frequency application emphasis availability ttl logic high low wide temperature range coming soon constant current medium medium wide temperature range coming soon high speed ? boost capacitor medium high fast switching production high speed ? boost inductor low high ul tra fast switching coming soon proportional lowest high wide drain current range coming soon pulsed power medium n/a pulse power coming soon a: static ttl logic driving the GA10JT12-247 may be driven using direct (5 v) ttl logic after current amplification. the (amplified) current level of the s upply must meet or exceed the steady state gate current (i g,steady ) required to operate the GA10JT12-247. the powe r level of the supply can be estimated from the target duty cycle of the particular application. i g,steady is dependent on the anticipated drain current id through the sjt and the dc current gain h fe , it may be calculated from the following equation. an accurate value of the h fe may be read from figure 6. , , 1.5 figure 22: ttl gate drive schematic b: high speed driving the sjt is a current controlled transistor which requires a positive gate current for turn-on as well as to remain in on-state. an ideal gate current waveform for ultra-fast switching of the sjt, while ma intaining low gate drive losses, is shown in figure 23 which feat ures a positive current peak during turn-on, a negative current peak dur ing turn-off, and continuous gate current to remain on. figure 23: an idealized gate current waveform for fast switching of an sjt. an sjt is rapidly switched from its blocking state to on-state, when the necessary gate charge, q g , for turn-on is supplied by a burst of high gate current, i g,on , until the gate-source capacitance, c gs , and gate-drain capacitance, c gd , are fully charged. ,
GA10JT12-247 nov 2014 http://www.genesicsemi.com/commercial- sic/sic-junction-transistors/ pg8 of 11 ideally, i g,pon should terminate when the drain voltage falls to its on-state value in order to avoid unnecessary drive losses during the stea dy on-state. in practice, the rise time of the i g,on pulse is affected by the parasitic inductances, l par in the device package and drive circuit. a voltage developed across the parasitic i nductance in the source path, l s , can de-bias the gate-source junc tion, when high drain currents begin to flow through the device. the voltage applied to the gate pin should be maintained high enough, above the v gs,sat (see error! reference source not found. ) level to counter these effects. a high negative peak current, -i g,off is recommended at the start of the turn-off transition, in order to rapidly sweep out the injected carriers from the gate, and achieve rapid turn-off. while sati sfactory turn off can be achieved with v gs = 0 v, a negative gate voltage v gs may be used in order to speed up the turn-off transition. two high-speed drive topologies for t he sic sjts are presented below. b:1: high speed, low loss drive with boost capacitor, ga03iddjt30-fr4 the GA10JT12-247 may be driven using a high speed, low loss drive with boost capacitor topology in which multiple voltage level s, a gate resistor, and a gate capacitor are used to provide fast switchi ng current peaks at turn-on and turn-off and a continuous gate c urrent while in on-state. a 3 kv isolated evaluation gate drive board (ga03iddjt30- fr4) utilizing this topology is commercially available for h igh and low- side driving, its datasheet provides additi onal details about this drive topology. figure 24: topology of the ga03iddjt30-fr4 two voltage source gate driver. the ga03iddjt30-fr4 evaluation board comes equipped with two on boar d gate drive resistors (rg1, rg2) pre-installed for an effe ctive gate resistance 3 of r g = 3.75 ? . it may be necessary for the user to reduce rg1 and rg2 under high drain current conditions for safe operation of the GA10JT12-247. the steady state current supp lied to the gate pin of the GA10JT12-247 with on-board r g = 3.75 ? , is shown in figure 25. the maximum allowable safe value of r g for the user?s required drain curr ent can be read from figure 26. for the GA10JT12-247, r g must be reduced for i d ~10 a for safe operation with the ga03iddjt30-fr4 . for operation at i d ~10 a, r g may be calculated from the following equat ion, which contains the dc current gain h fe (figure 6) and the gate- source saturation voltage v gs,sat (figure 7). , 4.7 , , 1.5 0.6?
GA10JT12-247 nov 2014 http://www.genesicsemi.com/commercial- sic/sic-junction-transistors/ pg9 of 11 figure 25: typical steady state gate current supplied by the ga03iddjt30-fr4 board for the GA10JT12-247 with the on board resistance of 3.75 ? figure 26: maximum gate resistance for safe operation of the GA10JT12-247 at different drain currents using the ga03iddjt30-fr4 board. b:2: high speed, low loss drive with boost inductor a high speed, low-loss driver with boost inductor is also capabl e of driving the GA10JT12-247 at high-speed. it utilizes a gate drive inductor instead of a capacitor to provide the high-current gate current pulses i g,on and i g,off . during operation, inductor l is charged to a specified i g,on current value then made to discharge i l into the sjt gate pin using logic control of s 1 , s 2 , s 3 , and s 4 , as shown in figure 27. after turn on, while the device remains on the necessary steady state gate current i g,steady is supplied from source vcc through rg. please refer to the article ?a current-source concept for fast and efficient driving of silicon carbide transistors? by dr. jacek r ? bkowski for additional information on this driving topology. 4 figure 27: simplified inductive pulsed drive topology 3 ? r g = (1/rg1 +1/rg2) -1 . driver is pre-installed with rg1 = rg2 = 7.5 ? 4 ? archives of electrical engineering. volume 62, issue 2, pages 333?343, issn (print) 0004-0746, doi: 10.2478/aee-2013-0026, j une 2013
GA10JT12-247 nov 2014 http://www.genesicsemi.com/commercial- sic/sic-junction-transistors/ pg10 of 11 c: proportional gate current driving for applications in which the GA10JT12-247 will operate over a wi de range of drain current conditions, it may be beneficial to drive the device using a proportional gate drive topology to optimize gate driv e power consumption. a proportional gate driver relies on instant aneous drain current i d feedback to vary the steady state gate current i g,steady supplied to the GA10JT12-247 c:1: voltage controlled proportional driver the voltage controlled proportional driver relies on a gate dr ive ic to detect the GA10JT12-247 drain-source voltage v ds during on-state to sense i d . the gate drive ic will then increase or decrease i g,steady in response to i d . this allows i g,steady , and thus the gate drive power consumption, to be reduced while i d is relatively low or for i g,steady to increase when is i d higher. a high voltage diode connected between the drain and sense protects the ic from high- voltage when the driver and GA10JT12-247 are in off-state. a simplified version of th is topology is shown in figure 29, additional information w ill be available in the future at http:// www.genesicsemi.com/commercial-sic/sic-jun ction-transistors/ figure 28: simplified voltage controlled proportional driver c:2: current controlled proportional driver the current controlled proportional driver re lies on a low-loss transformer in the drai n or source path to provide feedback i d of the ga10jt12- 247 during on-state to supply i g,steady into the device gate. i g,steady will then increase or decrease in response to i d at a fixed forced current gain which is set be the turns ratio of the transformer, h force = i d / i g = n 2 / n 1 . GA10JT12-247 is initially tuned-on using a gate current pulse supplied into an rc drive circuit to allow i d current to begin flowing. this topology allows i g,steady , and thus the gate drive power consumption, to be reduced while i d is relatively low or for i g,steady to increase when is i d higher. a simplified version of this topology is shown in figure 29, additional information will be available in the future at http ://www.genesicsemi.com/commercial- sic/sic-junction-transistors/. figure 29: simplified current controlled proportional driver
GA10JT12-247 nov 2014 http://www.genesicsemi.com/commercial- sic/sic-junction-transistors/ pg11 of 11 section vii: package dimensions to-247 package outline note 1. controlled dimension is inch. di mension in bracket is millimeter. 2. dimensions do not include end fl ash, mold flash, material protrusions revision history date revision comments supersedes 2014/11/12 1 updated electric al characteristics 2014/08/25 0 initial release published by genesic semiconductor, inc. 43670 trade center place suite 155 dulles, va 20166 genesic semiconductor, inc. reserves right to make changes to the product specificat ions and data in this document without noti ce. genesic disclaims all and any warranty and liability arising out of use or application of any product. no license, express or i mplied to any intellectual property rights is granted by this document. unless otherwise expressly indicated, genesic products are not designed, tested or authorized for use in life-saving, medical, aircraft navigation, communication, air traffic cont rol and weapons systems, nor in applications where their failure may result in death , personal injury and/or property damage. (15.748) (16.256) 0.620 0.640 ? 0.140 (3.556) 0.143 (3.632) 0.065 (1.651) 0.083 (2.108) 0.040 (1.016) 0.055 (1.397) 0.2146 (5.451) bsc. 0.016 (0.406) 0.031 (0.787) 0.059 (1.498) 0.098 (2.489) 0.171 (4.699) 0.208 (5.283) 0.075 (1.905) 0.115 (2.921) (4.318 ref.) 0.170 ref. (5.486) 0.216 0.819 0.844 (20.803) (21.438) 0.780 0.800 (19.812) (20.320) 0.177 max (4.496) 0.242 bsc. (6.147 bsc.) ? 0.118 (3.00) 0.22 (5.59) ? 0.283 (7.19) 0.652 (16.56 ) 0.55 (13.97) 0.236 (5.99) 0.054 (1.36) 0.012 (0.3) 0.045 (1.14) GA10JT12-247 xxxxxx lot code
GA10JT12-247 aug 2014 http://www.genesicsemi.com/comme rcial-sic/sic-junction-transistors/ pg 1 of 1 section viii: spice model parameters this is a secure document. please copy this code from the spice model pdf file on our website (http://www.genesicsemi.com/images/products_sic /sjt/GA10JT12-247_spice.pdf) into ltspice (version 4) software for simulation of the GA10JT12-247. * model of genesic semiconductor inc. * * $revision: 2.0 $ * $date: 25-aug-2014 $ * * genesic semiconductor inc. * 43670 trade center place ste. 155 * dulles, va 20166 * * copyright (c) 2014 genesic semiconductor inc. * all rights reserved * * these models are provided "as is, where is, and with no warranty * of any kind either expressed or implied, including but not limited * to any implied warranties of merchantability and fitness for a * particular purpose." * models accurate up to 2 times rated drain current. * .model ga10jt12 npn + is 5.00e-47 + ise 1.26e-28 + eg 3.23 + bf 85 + br 0.55 + ikf 5000 + nf 1 + ne 2 + rb 4.67 + irb 0.001 + rbm 0.16 + re 0.005 + rc 0.099 + cjc 427.39e-12 + vjc 3.1004 + mjc 0.4752 + cje 1373e-12 + vje 10.6442 + mje 0.21376 + xti 3 + xtb -1.27 + trc1 6.8e-3 + vceo 1200 + icrating 10 + mfg genesic_semiconductor * * end of ga10jt12 spice model

▲Up To Search▲

Price & Availability of GA10JT12-247

	To Download GA10JT12-247 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .